RESEARCH BRIEF
What changes when we design the compute itself?
Custom FPGA architectures for AI acceleration, efficient memory systems, and hardware–software co-design.
This HARD Lab direction studies the problem as an end-to-end system rather than as a single model demo. Current related work provides useful building blocks and baselines [1] [2] [3] [4] [5]; the lab’s goal is to connect them into measurable, reproducible research artifacts.
Transformer inference and custom parallel datapaths
PCIe–DDR4 data movement and memory-system design
Network-accessible hardware and system interfaces
PROPOSED WORKFLOW
Build, measure, iterate.
Architect
Identify the model operations, memory traffic, and interfaces that should shape the hardware architecture.
Implement
Build and integrate compute datapaths, memory controllers, and host or network interfaces on the FPGA.
Measure
Evaluate correctness, resource use, throughput, and latency on the actual platform.
STUDENT ENTRY POINTS
Ways to start contributing.
- Transformer inference and custom parallel datapaths
- PCIe–DDR4 data movement and memory-system design
- Network-accessible hardware and system interfaces
RELATED WORK / 2026-09-10
Selected papers & citations.
Five primary-source papers selected to frame this direction. Links point to the authors’ arXiv records; these are external works, not HARD Lab publications.
5 selected papers · newest first by initial submission
FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill
Co-designs dynamic sparse attention, sparse-index handling, and on-chip caching for long-context prefill on an FPGA.
Why it matters here. A reference for prefill-specific architecture. The reported AMD Alveo platform differs from the lab’s Intel Stratix 10 target; porting is a research task.
Full citation & BibTeX
Rakshith Jayanth, Viktor Prasanna (2026). FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill. arXiv:2602.20515. https://doi.org/10.48550/arXiv.2602.20515
@misc{hardlab_fast_prefill,
title = {{FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill}},
author = {Rakshith Jayanth and Viktor Prasanna},
year = {2026},
eprint = {2602.20515},
archivePrefix = {arXiv},
doi = {10.48550/arXiv.2602.20515},
url = {https://arxiv.org/abs/2602.20515},
note = {External related work; metadata checked 2026-09-10}
}FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
Explores a composable high-level-synthesis library and hybrid accelerator design for different LLM inference stages.
Why it matters here. Motivates reusable operator interfaces, separate prefill/decode measurements, and a modular hardware design flow.
Full citation & BibTeX
Jiahao Zhang et al. (2026). FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design. arXiv:2601.15710. https://doi.org/10.48550/arXiv.2601.15710
@misc{hardlab_flexllm,
title = {{FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design}},
author = {Jiahao Zhang and Zifan He and Nicholas Fraser and Michaela Blott and Yizhou Sun and Jason Cong},
year = {2026},
eprint = {2601.15710},
archivePrefix = {arXiv},
doi = {10.48550/arXiv.2601.15710},
url = {https://arxiv.org/abs/2601.15710},
note = {External related work; metadata checked 2026-09-10}
}LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs
Investigates memory-based lookup computation and quantization as an alternative to conventional arithmetic-heavy LLM inference.
Why it matters here. Suggests experiments trading DSP use against lookup storage, accuracy, bandwidth, and latency on the actual board.
Full citation & BibTeX
Zifan He et al. (2025). LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs. arXiv:2511.06174. https://doi.org/10.48550/arXiv.2511.06174
@misc{hardlab_lut_llm,
title = {{LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs}},
author = {Zifan He and Shengyu Ye and Rui Ma and Yang Wang and Jason Cong},
year = {2025},
eprint = {2511.06174},
archivePrefix = {arXiv},
doi = {10.48550/arXiv.2511.06174},
url = {https://arxiv.org/abs/2511.06174},
note = {External related work; metadata checked 2026-09-10}
}Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA
Studies LLM accelerator design under embedded-FPGA resource and memory constraints.
Why it matters here. Useful background for resource budgeting and for separating compute limits from external-memory bottlenecks.
Full citation & BibTeX
Jindong Li et al. (2025). Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA. arXiv:2507.03308. https://doi.org/10.48550/arXiv.2507.03308
@misc{hardlab_hummingbird,
title = {{Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA}},
author = {Jindong Li and Tenglong Li and Ruiqi Chen and Guobin Shen and Dongcheng Zhao and Qian Zhang and Yi Zeng},
year = {2025},
eprint = {2507.03308},
archivePrefix = {arXiv},
doi = {10.48550/arXiv.2507.03308},
url = {https://arxiv.org/abs/2507.03308},
note = {External related work; metadata checked 2026-09-10}
}FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
Presents an FPGA mapping flow combining sparse computation, mixed precision, and memory-system design for LLM inference.
Why it matters here. A systems-level baseline: the compiler, host interface, memory layout, and accelerator must be evaluated together.
Full citation & BibTeX
Shulin Zeng et al. (2024). FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs. arXiv:2401.03868. https://doi.org/10.48550/arXiv.2401.03868
@misc{hardlab_flightllm,
title = {{FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs}},
author = {Shulin Zeng and Jun Liu and Guohao Dai and Xinhao Yang and Tianyu Fu and Hongyi Wang and Wenheng Ma and Hanbo Sun and Shiyao Li and Zixiao Huang and Yadong Dai and Jintao Li and Zehao Wang and Ruoyu Zhang and Kairui Wen and Xuefei Ning and Yu Wang},
year = {2024},
eprint = {2401.03868},
archivePrefix = {arXiv},
doi = {10.48550/arXiv.2401.03868},
url = {https://arxiv.org/abs/2401.03868},
note = {External related work; metadata checked 2026-09-10}
}No selected papers match this filter.